Microprocessing devices often need access to external memory to store data and program instructions. In some devices, the memory device is external to the package and communicates with the microprocessor through an external interface. As memory requirements continues to increase, additional memory devices are often required to meet speed and bandwidth requirements. Interfacing to the external memory devices requires more pins on the package, as well as additional space within the equipment in which the microprocessor and memory devices are being used. The additional memory device may therefore result in a relatively significant increase in cost. A more cost efficient alternative would be to stack the additional memory device inside the package with the microprocessor.
Microprocessor and memory devices are typically configured on a silicon wafer referred to as a die. Several dies may be stacked in a single package and sold as an integrated circuit. Pins are located outside the package to allow the devices in the package to be electrically coupled with other devices. While some of the pins may be allocated for external interfaces to test the dies in the package, it is typically desirable to allocate as many of the pins as possible to other types of signals, such as control, data, power, and ground signals.
As integrated circuit technology scales down, the supply voltage must be reduced to prevent breakdown of gate insulators in electronic components. Voltage reduction has the added benefit of reducing the dynamic power consumption in an integrated circuit. Voltage downscaling also results, however, in a linear increase in the propagation delay of the logic gates. Therefore, the threshold voltage of the transistors must be lowered to maintain the circuit speed. This reduction in threshold voltage results in a significant increase in the leakage current, which increases the static power consumption in the circuit.
Each of the dies in the stack is typically tested comprehensively before packaging. The dies can potentially be damaged during assembly, however, and additional testing must be performed once the dies are packaged together. Most failures are due to mechanical stress and/or electrostatic discharge, which can cause additional leakage current at one or more of the pins. Leakage current can drain power supplies in battery powered devices more rapidly than necessary. It is therefore desirable to test packaged devices under expected operating conditions at the package level to insure the devices are performing within allowable parameters.
Most suppliers of integrated circuit devices stack memory dies to eliminate the external memory devices altogether. Such configurations leave the external interface pins unused. Accordingly, the unused pins can be tied to the stacked memory interface, allowing full access to the stacked device at package level for comprehensive testing.
In some configurations, however, an external memory system can be supplemented with a stacked memory die. As a result, there are no spare pins available on the package to access the memory signals of the stacked die. Since there are no dedicated pins, some pins on the package are shared between the stacked die signals along with signals on the main die.
FIG. 1 shows one known configuration of an electronic component package 100 that allows testing of a main die 102 and a stacked die 104. Special test pads 106 are added to the stacked die 104 and are bonded to external pins 108 on the package 100 along with other functional pads 110 of the main die 102. The stacked die test pads 106 are disabled during normal functional mode, while the functional pads 110 on the main die 102 are disabled in test mode. One drawback of this configuration of package 100 is the addition of extra test pads 106 on the stacked die 104, which adds extra cost.
FIG. 2 shows another electronic component package 200 that allows testing of main die 202 and stacked die 204 without requiring the special test pads 106. Instead, analog multiplexers 206 are coupled to combine the signals output to the functional pads 210, 212 of the main die 202 with signals from die-to-die functional pads 208 of the stacked die 204. The multiplexed signals 210, 212 are coupled to respective pins 214, 216 of the package 200. Package 200 allows the stacked die 204 to be tested, but the analog multiplexers 206 must be very large in order to support high speed operation. This not only significantly impacts the speed at which the dies 202, 204 can be tested, but also adds a huge load on the test die-to-die pads 208. The load impacts the speed of operation during normal mode. In summary, while the package 200 allows full test of the stacked die 204 for functionality as well as pin leakage, the testing speed as well as speed during normal operation would be severely restricted by the large analog multiplexers 206.
It is therefore desirable to provide electronic component packages with stacked dies that can be comprehensively tested while alleviating the drawbacks associated with known solutions.